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ISL6411
November 2003 FN9081.2
Triple Output, Low-Noise LDO Regulator with Integrated Reset Circuit
The ISL6411 is an ultra low noise triple output LDO regulator with microprocessor reset circuit and is optimized for powering wireless chip sets. The IC accepts an input voltage range of 3.0V to 3.6V and provides three regulated output voltages: 1.8V (LDO1), 2.84V (LDO2), and another ultra clean 2.84V (LDO3). On chip logic provides sequencing between LDO1 and LDO2 for BBP/MAC and I/O supply voltage outputs. LDO3 features ultra low noise that does not typically exceed 30V RMS to aid VCO stability. High integration and the thin Quad Flat No-lead (QFN) package makes ISL6411 an ideal choice to power many of today's small form factor industry standard wireless cards, such as PCMCIA, mini-PCI and Cardbus-32. The ISL6411 uses an internal PMOS transistor as the pass device. The SHDN pin controls LDO1 and LDO2 outputs whereas SHDN3 controls LDO3 output. Internal voltage sequencing insures that LDO1 output (1.8V supply) is always stabilized before LDO2 is turned on. When powering down, power to the LDO2 is removed before the LDO1 output goes off. The ISL6411 also integrates RESET function, which eliminates the need for additional RESET IC required in WLAN applications. The IC asserts a RESET signal whenever the VIN supply voltage drops below a preset threshold, keeping it asserted for at least 25ms after Vin has risen above the reset threshold. An output fault detection circuit indicates loss of regulation on any of the three outputs. Other features include an over current protection, thermal shutdown and reverse battery protection.
Features
* Small DC-DC Converter Size - Three LDOs and RESET Circuitry in a Low-Profile 4x4mm QFN Package * High Output Current - LDO1, 1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA - LDO2, 2.84V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA - LDO3, 2.84V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA * Ultra-Low Dropout Voltage - LDO2, 2.84V. . . . . . . . . . . . . . . 125mV (typ.) at 300mA - LDO3, 2.84V. . . . . . . . . . . . . . . 100mV (typ.) at 200mA * Ultra-Low Output Voltage Noise - <30VRMS (typ.) for LDO3 (VCO Supply) * Stable with Smaller Ceramic Output Capacitors * Voltage Sequencing for BBP/MAC and Analog Supplies * Extensive Protection and Monitoring Features - Over current protection - Short circuit protection - Thermal shutdown - Reverse battery protection - FAULT indicator * Logic-Controlled Dual Shutdown Pins * Integrated Microprocessor Reset Circuit - Programmable Reset Delay - Complimentary Reset Outputs * Proven Reference Design for Total WLAN System Solution * QFN Package Option - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - Near Chip-Scale Package Footprint Improves PCB Efficiency and Is Thinner in Profile - Lead-Free Package Option Available ("Z" suffix)
Ordering Information
PART NUMBER ISL6411IR ISL6411IRZ (Note) TEMP. RANGE (oC) -40 to +85 -40 to +85 PACKAGE 16 Ld QFN 16 Ld QFN PKG. DWG. # L16.4x4 L16.4x4
NOTE: " Z " Suffix: Intersil Lead Free products employ special lead free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and lead free soldering operations. Intersil Lead Free products are MSL classified at lead free peak reflow temperatures that meet or exceed the lead free requirements of IPC/JEDEC J Std-020B. Tape and Reel available. Add "-T" suffix for tape and reel packing option (e.g., ISL6411RZ-T for lead free tape and reel).
Applications
* PRISM(R) 3, PRISM GTTM, and PRISM WWR Chipsets * WLAN Cards - PCMCIA, Cardbus32, MiniPCI Cards - Compact Flash Cards * Hand-Held Instruments
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. PRISM(R) 3 and PRISM GTTM are trademarks of GlobespanVirata, Inc. All other trademarks mentioned are the property of their respective owners.
ISL6411 Pinout
ISL6411 (QFN) TOP VIEW
RESET FAULT
VIN 14
16 RESET CT SHDN SHDN3 1 2 3 4 5 OUT3
15
VIN 13 12 OUT1 11 CC1 10 OUT2 9 CC2 8 GND
6 CC3
7 GND3
Typical Application Schematic
+3.3V VIN
+ C8 3.3F 14 VIN 13 VIN 16 15
RESET
FAULT
+1.8V VOUT1 +2.84V VOUT2
C4 0.033F C3 0.033F C2 3.3F C1 3.3F
C7 0.01F
1 2 3 4
RESET CT SHDN SHDN3
ISL6411
12 OUT1 11 CC1 10 OUT2 9 CC2
+2.84V VOUT3
C5 3.3F
5 6 7 8 E E C6 0.033F
2
OUT3 CC3 GND3 GND
ISL6411 Functional Block Diagram
Gm VIN 13
VIN + LDO1 BAND GAP REF. 1.2V OUT1
14
12
WINDOW COMP
CC1 Gm THERMAL SHUT DOWN 150oC + LDO2 15 FAULT WINDOW COMP OUT2
11
VIN
10
VIN Gm CONTROL LOGIC 3 SHDN + 4 SHDN3 LDO3
CC2
9
OUT3
5
ENABLES 2 CT
WINDOW COMP
16
RESET
RESET CC3 6
1
RESET
8
GND
GND3
7
3
ISL6411 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.35 1.95 1.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.65 BSC 0.60 16 4 4 0.60 12 0.75 0.15 2.25 2.25 0.38 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 4 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12

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